Enhancement-mode III-N devices, circuits, and methods

ABSTRACT

A method of fabricating AlGaN/GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN/GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the gate metal to the plasma treated AlGaN/GaN heterostructure surface; 4) lifting off the metal except the gate electrode; and 5) high temperature post-gate annealing of the sample. This method can be used to shift the threshold voltage of a HFET toward a more positive value, and ultimately convert a depletion-mode HFET to an enhancement-mode HFET (E-HFET).

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority from U.S. Provisional Patent Application No. 60/740,256 filed on Nov. 29, 2005, and also from U.S. Provisional Patent Application No. 60/748,339 filed on Dec. 8, 2005, both of which are hereby incorporated by reference.

BACKGROUND AND SUMMARY OF THE INVENTION

The present application relates to structures and methods of fabricating enhancement-mode heterostructure field effect transistors (“HFETs”), and in particular, to aluminum-gallium-nitride/gallium-nitride (“AlGaN/GaN”) enhancement-mode HFETs. Group III-nitride (“III-N”) compound semiconductors, such as those incorporating AlGaN/GaN, possess the advantages of having wide bandgap, high breakdown field, and large thermal conductivity, which can bring significant benefits to the design of heterostructure field-effect transistors and applications ultilizing HFETs. Because their high power handling capabilities, AlGaN/GaN HFETs can be used for radio frequency/microwave power amplifiers and high power switches. However, most power amplifiers and switches using AlGaN/GaN HFETs feature depletion-mode (“D-mode”) HFETs as the building block. Since a D-mode HFET is a transistor with a negative value for the threshold voltage (“V_(th)”), D-mode HFETs need both a positive and negative voltage bias to be turned on and off. If an enhancement-mode (“E-mode”) HFET could be made available, only a positive voltage supply would be needed for circuit applications, resulting in simplified circuits and reduced costs.

Furthermore, owing to the wide bandgap of the GaN-based semiconductor materials, AlGaN/GaN HFETs are capable of high-temperature operation (potentially up to 600° C.), and are thus suitable for high-temperature integrated circuits, such as required in aviation and automotive applications. Further, for HFET-based logic circuits, the direct-coupled field effect transistor logic (“DCFL”) features the simplest configuration. In DCFLs, E-mode HFETs are used as drivers while D-mode HFETs are used as the load.

Note that at zero gate bias, a D-mode HFET is capable of conducting current, and is called “normally-on” whereas for an E-mode HFET, the transistor is not conducting current, and is called “normally-off”.

FIG. 1 shows an E-mode HFET 10 using a thin AlGaN barrier layer 12, an undoped GaN layer 18, and a substrate layer 20, such as can be made from sapphire, silicon, or silicon carbide. With the help of the Schottky barrier 14 between the gate metal 16 and AlGaN barrier, the channel between source 22 and drain 24 can be pinched-off at zero gate bias as long as the AlGaN barrier is thin enough. However, E-mode HFET's fabricated in this manner have poor performance characteristics, such as low transconductance, large on-resistance, and high knee-voltage. This is due to high access resistance. As shown in FIG. 1, the access region between the gate and source also has very low carrier density because of the thin AlGaN barrier. Thus, the access region is also in the E-mode, which needs positive bias to be turned on. To produce E-mode HFETs with low access resistance, a “self-aligned” fabrication process is required, in which only the channel region directly under the gate electrode is in E-mode. Note that gates that are not self-aligned require overlap, which increases device size and stray capacitance.

There have been several attempts at fabrication of E-mode AlGaN/GaN high electron mobility transistors (“HEMTs”). Note that the terms “HEMT” and “HFET” are synonymous. Both are field effect transistors with the junction between two materials with different band gaps, e.g. a heterostructure as the channel. The effect of this heterostructure is to create a very thin layer where the Fermi energy is above the conduction band, giving the channel very low resistance, e.g. “high electron mobility”. As with all the other types of FETs, a voltage applied to the gate alters the conductivity of the thin layer.

Using a thin AlGaN barrier (10 nm), Khan et al. produced an E-mode HEMT with a peak transconductance of 23 mS/mm.

Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system was reported by Hu et al., “Enhancement mode AlGaN/GaN HFET with selectively grown PN junction gate,” April 2000, IEE Electronics Letters, Vol. 36, No. 8, pp. 753-754, which is hereby incorporated by reference in its entirety. In this work a selectively-grown P/N junction gate is used. The selectively-grown P-type layer is able to raise the potential of the channel and therefore deplete the carriers from the channel at zero gate bias. However, such an approach is not self-aligned and the problem of large access resistance persists.

Another attempt to fabricate an E-mode HFET in an AlGaN/GaN system was reported by Moon et al. who used inductivity couple plasma reactive ion etching (“ICP-RIE”) to carry out gate recess-etching. See Jeong S. MOon et al., “Submicron Enhancement-Mode AlGaN/GaN HEMTs,” June 2002, Digest 60th Device Research Conference, pp. 23-24, which is hereby incorporated by reference in its entirety.

Kumar et al. used a similar approach. Note that the AlGaN barrier under the gate can be thinned by the recess-etching and the threshold voltage is then raised to a positive value. However, ICP-RIE can cause serious damage to the AlGaN barrier and results in increased gate leakage current. To remove ICP-RIE induced damage, the recess-etching patterns must be removed and followed by high-temperature (about 700° C.) annealing. Thus, the gate patterns have to be created again through photo-lithography which cannot be accurately aligned with the recess-etching windows previously generated in the gate recess stage. Therefore, the process requires double photolithography, or alignment, and is not self-aligned. To ensure that the recess windows are fully covered by the gate electrodes, the gate electrodes need to be larger than the recess windows, resulting in a larger gate size, as mentioned earlier. Another problem associated with the ICP-RIE etching is the poor uniformity in the etching depth, which is undesirable for integrated circuits because it severely affects the uniformity in the threshold voltage.

Another approach used gate metals, e.g. Platinum (“Pt”) or Molybdenum (“Mo”), that have larger work function and have the tendency of reacting with III/V compound semiconductors. (Work function refers to the energy required to release an electron as it passes through the surface of a metal. For example, a Pt-based buried gate technology was previously used in realizing E-mode indium-aluminum-arsenide/indium-gallium-arsenide (“InAlAs/InGaAs”) HFETs. For AlGaN/GaN HFETs, Endoh et al. created an E-mode HFET from a D-mode HFET with a Pt-based gate electrode. Through high temperature gate annealing, the gate metal front can be made to sink into the AlGaN barrier and effectively reduce the barrier thickness and raise the threshold voltage to a positive value. Such an approach requires a D-mode HFET with a threshold voltage already close to zero because the sinking depth of the Pt-gate is limited. However, for monolithically-integrated E/D-mode HFET circuits, it is desirable for the D-mode HFET (which serves as the load) to have a more negative threshold voltage.

U.S. patent application Ser. No. 20030218183 entitled “High Power-Low Noise Microwave GaN Heterostructure Field Effect Transistor” to Miroslav Micovic et al., discloses a gate recess technique as one existing process technique to fabricate E-mode HFETs. However, in an AlGaN/GaN HFET, because of the lack of effective wet etching techniques, the recess etching is carried out by dry etching. For example, ICP-RIE is used for the recess etching, as mentioned earlier, with the accompanying severe damage and defects to the device.

U.S. patent application Ser. No. 2005059197 entitled “Semiconductor Device and Method for Manufacturing the Same” to Yoshimi Yamashita et al., discloses a technique usint the approach of using gate metals with larger work function for fabricating E-mode HFETs in GaN-based material systems. However, no metal has been found to have a work function larger than 1 electron volt (“eV”). As a result, in order to fabricate an E-mode HFET using the method of Yamashita et al., a sample which already exhibits a threshold voltage closer to zero volts is needed. This is not suitable for the integration of E-mode and D-mode HEMTs, which are both required for DCFL circuits.

III-N Enhancement-Mode Devices, Circuits, and Methods

The present application describes a new family of approaches to III-N device fabrication. According to various embodiments, fluorine ions are introduced into the wider-bandgap layer under the gate electrode as a step in the fabrication of a HEMT or the like. The implanted ions are substantially immobile and can effectively deplete the electrons in the channel underneath. Rapid thermal annealing as a further fabrication step fully repairs degradation of the carrier mobility in the channel without any other adverse effects to the HFETs. The resulting HFET has an access region between the source and gate electrodes that possesses high carrier density in the channel while maintaining low access resistance.

The disclosed innovations, in various embodiments, provide on or more of at least the following advantages:

-   -   Provides a self-aligned approach to fabricating E-mode AlGaN/GaN         HEMTs with low on-resistance, low knee-voltage, and high         extrinsic transconductance.     -   Allows for monolithic integration of enhancement-mode and         depletion-mode AlGaN/GaN HEMTs for the implementation of DCFL         circuits, with the simplest circuit configuration among several         choices.     -   Allows for a single positive polarity voltage supply for         radio-frequency and microwave front-end circuit blocks including         power amplifiers, low-noise amplifiers, mixers and oscillators.     -   Provides an E-mode HFET with a Vt several volts higher than a         AlGaN/GaN HFET not using the benefits of the present inventions.     -   Provides a method to manufacture self-aligned E-mode HFETs using         readily available microelectronic fabrication equipment.     -   Provides a method enabling the production of reproducible and         stable E-mode HEFT devices, particularly suitable for high         temperature digital circuit applications.     -   Provides a method enabling the production of         protection-circuit-free low-noise amplifiers.     -   Provides a method enabling the production of 1 μm-gate E-mode         HEMT with a high cutoff frequency     -   Provide a method for fabricating ehancement-mode         metal-insulator-semiconductor HFETs (MIS-HFETs) with more         positive threshold voltages and higher gate turn-on voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

The disclosed innovations will be described with reference to the accompanying drawings, which show important sample embodiments of the innovations and which are incorporated in the specification hereof by reference, wherein:

FIG. 1 shows a prior art E-mode HFET.

FIG. 2 shows transfer characteristics of a conventional D-mode HEMT, and E-mode HEMT without the benefit of the present innovations, and one embodiment of the present innovations.

FIGS. 3A through 3F show one embodiment of the present innovations illustrating the process of fabricating an E-mode AlGaN/GaN HEFT according to a first embodiment of the present innovations as illustrated in Example 1.

FIG. 4A shows I-V output characteristics for one embodiment of the present innovations as illustrated in Example 1.

FIG. 4B shows I_(g)-V_(gs) characteristics for one embodiment of the present innovations as illustrated in Example 1.

FIG. 5 shows fluorine ion concentration profiles as measured by “SIMS” for one embodiment of the present innovations as illustrated in Example 1.

FIG. 6 shows the cross section of one embodiment of the present innovations prior to implantation of fluorine ions as used in Example 1, 2 and 3.

FIG. 7 shows fluorine ion concentration profiles as measured by “SIMS” for various embodiments of the present innovations as illustrated in Example 2.

FIG. 7A shows fluorine ion concentration profiles as measured by “SIMS” for various embodiments of the present innovations as illustrated in Example 2A.

FIG. 7B shows fluorine ion concentration profiles as measured by “SIMS” for various embodiments of the present innovations as illustrated in Example 2A.

FIG. 8A shows the I_(d) versus V_(gs) transfer characteristics of various embodiments of the present innovations at different CF₄ plasma-treatment conditions as illustrated in Example 3.

FIG. 8B shows the g_(m) versus V_(gs) transfer characteristics of various embodiments of the present innovations at different CF₄ plasma-treatment conditions as illustrated in Example 3.

FIG. 9 shows the extracted barrier heights and ideality factors of gate Schottky diodes with different CF₄ plasma treatments for various embodiments of the present innovations as illustrated in Example 3.

FIG. 10 shows the V_(th) dependency on plasma power and treatment time for various embodiments of the present innovations as illustrated in Example 3.

FIG. 11 shows an AFM image depicting the insignificant etching effect of the CF₄ plasma treatment on the AlGaN layer for one embodiments of the present innovations as illustrated in Example 3.

FIG. 12A shows the DC I_(d) versus V_(gs) transfer characteristics for various embodiments of the present innovations as illustrated in Example 3.

FIG. 12B shows the DC g_(m) versus V_(gs) transfer characteristics for various embodiments of the present innovations as illustrated in Example 3.

FIG. 13 shows the DC output characteristics for one embodiment of the present innovations as illustrated in Example 3.

FIG. 14A shows both reverse and forward gate currents with different CF₄ plasma treatments for various embodiments of the present innovations as illustrated in Example 3.

FIG. 14B shows enlarged and forward gate currents with different CF₄ plasma treatments for various embodiments of the present innovations as illustrated in Example 3.

FIG. 15 shows dependencies of f_(t) and f_(max) on gate bias, where V_(ds) is fixed at 12V for one embodiment of the present innovations as illustrated in Example 3.

FIG. 16 shows on-wafer measured f_(t) and f_(max) with different CF₄ plasma treatments for various embodiments of the present innovations as illustrated in Example 3.

FIGS. 17A through 17F show on embodiment of the present innovations illustrating the process of fabricating an E-mode Si₃N₄AlGaN/GaN MISHFET according to the present innovations as illustrated in Example 4.

FIG. 18 shows the DC output characteristics of one embodiment of the present innovations as illustrated in Example 4.

FIG. 19A shows the transfer characteristics of on embodiment of the present innovations as illustrated in Example 4.

FIG. 19B shows the gate leakage currents of one embodiment of the present innovations as illustrated in Example 4.

FIG. 20 shows pulse measurements of one embodiment of the present innovations as illustrated in Example 4.

FIG. 21 shows small signal RF characteristics of one embodiment of the present innovations as illustrated in Example 4.

FIG. 22 shows simulated conduction-band diagrams of conventional D-mode AlGaN/GaN HEMT without CF₄ plasma treatment.

FIG. 23 shows simulated conduction-band diagrams of E-mode AlGaN/GaN HEMT with CF₄ plasma treatment.

FIG. 24 shows the electron concentration of a conventional D-mode AlGaN/GaN HEMT without CF₄ plasma treatment and an E-mode AlGaN/GaN HEMT with CF₄ plasma treatment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The numerous innovative teachings of the present application will be described with particular reference to the presently preferred embodiments (by way of example, and not limitation).

FIGS. 3A through 3F illustrate the process of fabricating an enhancement-mode III-nitride HFET according to a first embodiment of the present innovations. FIG. 3A illustrates a preferred epitaxial structure of the present innovations, where the reference numerals 110, 120, 130 and 140 denote substrate (e.g. sapphire, silicon or SiC), nucleation layer (low temperature grown GaN nucleation layer, AlGaN or AlN), high temperature-grown GaN buffer layer, and AlxGa1-xN barrier layer including the modulation doped carrier supply layer. The manufacturing method of enhancement mode III-nitride HFET of one embodiment is described below. The mesa isolation is formed using Cl₂/He plasma dry etching followed by the source/drain ohmic contact formation 160 with Ti, Al, Ni and Au annealed at 850° C. for 45 seconds as shown in FIG. 3B. Next, photoresist 170 is patterned with the gate windows exposed. Then, the fluorine ions are incorporated into Al_(x)Ga_(1-x)N barrier layer by, for examples, either fluorine plasma treatment or fluorine ions implantation as shown in FIG. 3C. The gate electrode 180 is formed on the barrier layer 140 by depositing and lift-off Ni and Au as shown in FIG. 3D. Thereafter, post-gate RTA is conducted at 400-450° C. for 10 minutes. A passivation layer 190 is grown on top of the wafer as shown in FIG. 3E. Finally, the contact pads are opened by removing portions of the passivation layer on the contact pads as shown in FIG. 3F.

EXAMPLE 1

An AlGaN/GaN HEMT structure was grown on a (0001) sapphire substrate in an Aixtron AIX 2000 HT metal-organic chemical vapor deposition (MOCVD) system. The HEMT structure consists of a low-temperature GaN nucleation layer, a 2.5-m-thick unintentionally doped GaN buffer layer and an AlGaN barrier layer with nominal 30% Al composition. The barrier layer consists of a 3-nm undoped spacer, a 15-nm carrier supplier layer doped at 2.5×10¹⁸ cm⁻³, and a 2-nm undoped cap layer. Room temperature Hall measurements of the structure yield an electron sheet density of 1.3×10¹³ cm⁻² and an electron mobility of 1000 cm²/Vs. The device mesa was formed using Cl₂/He plasma dry etching in an STS ICP-RIE system followed by the source/drain ohmic contact formation with Ti/Al/Ni/Au annealed ate 850° C. for 45 seconds. The ohmic contact resistance was typically measured to be 0.8 ohn-nm.

After gate windows with 1 nm length were opened by contact photolithography, the sample was treated by CF₄ plasma in an RIE system at an RF plasma power of 150 W for 150 seconds. Pressure of the treatment is typically 50 mTorr. The typical depth distribution profile of the fluorine ions thus incorporated via the treatment is Gaussian, and the typical depth when the fluorine concentration drops from the peak by one order of magnitude is 20 nm. Note that ion implantation is another method for incorporating the fluorine ions, and it is estimated that an energy of about 10 KeV would be required.

Ni/Au electron-beam evaporation and liftoff were carried out subsequently to form the gates electrodes. The plasma treated gate region and the gate electrode were self-aligned. Post-gate TRA was conducted at 400° C. for 10 minutes. This RTA temperature was chosen because RTA at temperatures higher than 500° C. can degrade both the gate Schottky contact and the source/drain ohmic contacts. The devices have a source-gate spacing of L_(5g)=1 μm and a gate-drain spacing of L_(gd)=2 μm. D-mode HEMTs were also fabricated on the same sample without plasma treatment to the gate regions.

FIG. 2 shows the transfer characteristics of both D-mode and E-mode (before and after post-gate annealing) AlGaN/GaN HEMTs. Defining V_(th) as the gate bias intercept of the linear extrapolation of drain current at the point of peak transconductance (g_(m)), the V_(th) of the E-mode device was determined to be 0.9 V, while the V_(th) of the D-mode device is −4.0 V. More than 4 V of V_(th) shift was achieved by the plasma treatment. At V_(gs)=0, the transconductance reaches zero, indicating a true E-mode operation. The drain current is well pinched-off and shows a leakage of 28 μA/mm at V_(ds)=6 V, the smallest value reported up to date for E-mode AlGaN/GaN HEMTs. The peak g_(m) is 151 mS/mm for the D-mode HEMT and 148 mS/mm for the E-mode HEMT, respectively. The maximum drain current (I_(max)) reaches 313 mA/mm at the gate bias (V_(gs)) of 3 V for the E-mode HEMT. Comparison of the current-voltage (I-V) characteristics of E-mode device before and after RTA suggests that RTA at 400° C. for 10 minutes plays an important role in recovering the damages induced during the plasma treatment and achieving high current density and transconductance. FIG. 4A shows the output curves of the E-mode device before and after the RTA process. No change in threshold voltage was observed after the RTA. At a V_(gs) of 2.5 V, the saturation drain current (247 mA/mm) of E-mode device after RTA at 400° C. is 85% higher than that (133 mA/mm) before RTA. and the knee voltage of the E-mode device with RTA is 2.2 V, where the drain current is 95% saturation drain current. The off-state drain breakdown voltage at V_(gs)=0V is larger than 80 V, showing no degradation compared to that observed in the D-mode HEMTs. FIG. 4B shows I_(g)/V_(gs) curves of these three devices. Lower gate leakage currents were achieved fro E-mode HEMT, especially after RTA.

In order to investigate the mechanisms of the V_(th) shift by CF₄ plasma treatment, secondary ion mass spectrum (SIMS) measurements were carried out on accompanying samples to monitor the atomic compositions changes of the CF₄ plasma treated AlGaN/GaN materials. In addition to Al, Ga, and N, significant amount of fluorine atoms were detected in the plasma treated sample. FIG. 5 shows the fluorine atom concentration profile of the sample treated at a CF₄ plasma power of 150 W for 2.5 minutes. The concentration of fluorine atoms is the highest near the AlGaN surface and drops by one order of magnitude in the channel. It can be deduced that the fluorine ions produced by the Cf₄ plasma were incorporated into the sample surface, similar to the effects of plasma immersion ion implantation (“PIII”), a technique developed to realize ultra-shallow junctions in advanced silicon technology. Because of the strong electro-negativity of the fluorine ions, the incorporated fluorine ions can provide immobile negative charges in the AlGaN barrier and effectively deplete the electrons in the channel. With enough fluorine ions incorporated in the AlGaN barrier, the D-mode HEMT can be converted to an E-mode HEMT. The CF₄ plasma treatment can result in a threshold voltage shift as large as 4.9 V. After RTA at 400° C. for 10 minutes, the peak fluorine atom concentration near the AlGaN surface is unchanged while that around the AlGaN/GaN interface experiences more significant reduction. It should be noted, however, SIMS measurement results from different runs do not offer accurate quantitive comparison because of the lack of reference criterion. Nevertheless, the minute change in V_(th) before and after RTA indicates that the total number of fluorine ions incorportated into the AlGaN barrier is near constant before and after RTA, while the plasma damages are significantly recovered by the RTA. The lower gate reverse leakage currents of an E-mode HEMT can be attributed to an upward band bending of the AlGaN layer as a result of fluorine ion incorporation. After the RTA process, the defects at the interface of metal and AlGaN induced by CF₄ were recovered, leading to further suppression of gate leakage current. From the atomic force microscopy (“AFM”) measurement conducted on a patterned sample, it was observed that the plasma treatment only results in a 0.8 nm reduction in the overall AlGaN barrier layer (20 nm thick).

On-wafer small-signal RF characteristics of D-mode and E-mode AlGaN/GaN HEMTs were measured from 0.1 to 39.1 GHz. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of both types of devices with 1 μm-long gate were derived from measured S-parameters as a function of frequency, as shown in FIG. 5. At V_(ds)=12 and V_(gs)=1.9 V, current gain cutoff frequency (f_(T)) of 10.1 GHz and a power gain cutoff frequency (f_(max)) of 34.3 GHz were obtained for the E-mode AlGaN/GaN HEMT, a little lower than that of its D-mode counterpart, whose and were measured at the drain bias of 12 V and gate bias of −3 V to be 13.1 GHz, respectively.

One advantage of the present innovations is that the E-mode HFET with fluorine ions incorporated in barrier layer can stand a larger gate bias (>3V) corresponding to a larger input voltage swing.

Also, thermal reliability testing has shown that the fluorine ion incorporation in the AlGaN barrier is stable up to 700° C. However, Schottky contact, made of nickel, is only stable up to 500° C. Therefore, the application temperature range is up to 500° C. unless another Schottky contact technique is used. Tungsten gate is one open possible candidate.

In FIG. 7, the effect of different post-gate RTA's on the fluorine atoms' distributions in AlGaN/GaN heterostructures, as measured by SIMS, is shown. The untreated device is used as a reference.

It was found that the fluorine ions, which were incorporated into AlGaN barrier layer by CF₄ plasma treatment, could effectively shift the threshold voltage positively. The fluorine ions' incorporation in the AlGaN layer was confirmed by secondary-ion-mass-spectrum (SIMS) measurements, as shown in FIG. 7. During CF₄ plasma treatment, fluorine ions are implanted into AlGaN/GaN heterostructure in a self-built electrical field stimulated by the RF power.

It is also concluded from the results shown in FIG. 7 that the implanted fluorine ions have a good thermal stability in the AlGaN layer up to 700° C. Deep-level transient spectroscopy (“DLTS”) has been conducted on the HEMT samples treated by CF₄ plasma. The fluorine ions incorporated in the AlGaN barrier appear to introduce a deep-level state that is at least 1.8 eV below the conduction-band minimum. As a result, the fluorine ions are believed to introduce a negatively charged acceptor-like deep level in the AlGaN.

Note that in SIMS plots such as FIG. 7, it is difficult to make accurate calculation of concentration from SIMS measurement because the beam size is not known. However, based on the band structure and the threshold voltage calculation, the peak value of the F concentration can be as high as about 1×20 cm⁻³.

Recent DLTS and photo-conductivity experiments have revealed that the incorporation of fluorine ions in the AlGaN layer is predominantly substitutional, with the fluorine atoms filling nitrogen vacancies in the AlGaN layer.

In FIG. 7A, the effect of different plasma power levels without RTA on the fluorine atoms' distribution in AlGaN/GaN heterostructures, as measured by SIMS, is shown.

Note that the 200 W and 400 W lines show a “bump” at the interface between the AlGaN/GaN interface. During an incorporation process, the fluorine ions can fill up surface or interface states (or “traps”), producing “anomalous stopping”. Therefore, this indicates there are more traps at the interface. Further, the 600 W and 800 W lines do not show the bump most likely because of the greater penetration depth and overall concentration.

The untreated device is used as a reference. In FIG. 7B, the effect of different post-gate treatment temperatures at a fixed power of 600 W for RTA on the fluorine atoms' distributions in AlGaN/GaN heterostructures, as measured by SIMS, is shown. The untreated device is used as a reference. Note that the distributions in the AlGaN for 700° C. and below show a normal effect of root Dt, but the distribution in the AlGaN layer seems to reflect a very different diffusivity (or perhaps some other activation energy effect). Thus, the data indicates that fluorine ions are more stable in AlGaN than in GaN. Further, the building energy can be higher, and the fluorine-related energy states are deeper below the conduction band in AlGaN than in GaN.

Sensitivity to plasma treatment parameters was also investigated. Devices were fabricated with different V_(th) values by applying different CF₄ plasma power and treatment times. Five different combinations were used: 100 W for 60 seconds, 150 W for 20 seconds, 150 W for 60 seconds, 150 W for 150 seconds, and 200 W for 60 seconds. For comparison, an HEMT without CF₄ treatment was also fabricated on the same sample and in the same processing run. All devices were unpassivated in order to avoid any confusion caused by the passivation layer, which may change the stress in the AlGaN layer and alter the piezoelectric polarization. All the HEMT devices have a gate length of 1 μm, a source-gate spacing of L_(sg)=1 μm and a gate-drain spacing of L_(gd)=2 μm. DC current-voltage (I-V) characteristics of the fabricated devices were measured using an HP4156A parameter analyzer. Transfer characteristis and transconductance (g_(m)) characteristics are shown in FIGS. 8A and 8B, respectively. Taking the conventional HEMT (i.e., without CF₄ plasma treatment) as the baseline devices, the threshold voltage of all the other CF₄ plasma-treated HEMTs are shifted to the positive direction. Defining V_(th) as the gate-bias intercept of the linear extrapolation of the drain-current at the point of peak transconductance (g_(m)), the V_(th) of all the devices were extracted and the listed in FIG. 9. For the conventional HEMT, V_(th) is −4 V. For the HEMT treated by CF₄ plasma at 150 W for 150 seconds, the V_(th) is 0.9 V, which corresponds to the E-mode HEMT. A maximum V_(th) shift of 4.9 V was achieved. In order to further reveal the effects of CF₄ plasma treatment, the dependencies of V_(th) on both CF₄ plasma treatment time and RF power are plotted in FIG. 10. As the plasma power is increased and as longer treatment time are utilized, larger shifts in V_(th) are effected. With the increase in the plasma treatment time, more fluorine ions were implanted into AlGaN layer. The increased fluorine ion concentrations leads to a reduced electron density in the channel, and causes the positive shift of the V_(th). When the plasma power increases, fluorine ions obtain a higher energy and fluorine ion flux increases due to the enhanced ionization rate of CF₄, With higher energy, fluorine ions can reach at a deeper depth closer to the channel. The closer the fluorine ions are to the channel, the more effective they at delpleting 2DEG, and a larger shift in V_(th) is achieved. The increased fluorine ions flux has the same effect on V_(th) as the increase of the plasma treatment time by raising the fluorine atoms concentration in AlGaN layer. It should be noted that the nearly linear V_(th) versus time and V_(th) versus power relationships imply the possibilities of a precise control of V_(th) of AlGaN/GaN HEMTs. Although the V_(th) is shifted by CF₄ plasma treatment, the gm is not degraded. As shown in FIG. 8B, all the devices' maximum g_(m) are in the range of 149-166 mS/mm, except for that treated at 150 W for 60 seconds, which has a higher peak gm of 186 mS/mm. It is suspected that this singularity point was caused by the non-uniformity in epitaxial growth. Confirmed by an AFM measurement conducted on a CF₄-treated patterned sample (with part of the sample treated and other parts protected from the plasma treatment), the CF₄ plasma treatment only results in an AlGaN-thickness reduction of less than 1 nm, as shown in FIG. 11. Thus, the almost constant transconductance indicates that the 2DEG mobility in the channel is maintained in the device fabrication according to the present innovations. A key step in maintaining the transconductance is the post-gate annealing process.

Recovery of Plasma-Induced Damages by Post-Gate Annealing

As previously discussed, the plasma normally induces damages and creates defects in semiconductor materials, and consequently degrades carriers' mobility. RTA is an effective method to repair these damages and recover the mobility. In the CF₄ plasma-treated AlGaN/GaN HEMTs, drain-current and transconductance degradation occurs just after the plasma treatment. In FIGS. 12A and 12B, the drain-current and transconductance measured on an untreated device and a treated device (200 W, 60 seconds) before and after RTA (400° C. for 10 minutes) are plotted. FIG. 13 compares the output characteristics of the treated device before and after RTA. The drain-current was 76% and the transconductance was 51% higher after the RTA in the treated device. The RTA process can recover majority of the mobility degradation in the plasma-treated device, while showing an insignificant effect on the conventional untreated device. Therefore, the recovery of I_(d) and g_(m) in the CF₄ plasma-treated device is the result of the effective recovery of the 2DEG mobility at this RTA condition. Compared to a higher annealing temperature of 700° C., which is needed to recover damages induced by chlorine-based ICP-RIE in the case of recessed gate, this lower RTA temperature implies that the CF₄ plasma treatment creates lower damages than the chlorine-based ICP-RIE. It also enables the RTA process to be carried out after the gate deposition, fulfilling the goal of a self-aligned process. If the previous definition of V_(th) is used, the V_(th) of the CF₄ plasma-treated device seems to be shifted from 0.03 to −0.29 V after the RTA. When the start point of g_(m), as shown in FIG. 12B, or the start point of I_(d) at the logarithm scale, as shown in the inset of FIG. 12A, is used as the criteria to evaluate V_(th), the V_(th) of the CF₄ plasma-treated device is not changed after the RTA. The good thermal stability of V_(th) is consistent with the previously mentioned good thermal stability of fluorine atoms in AlGaN layer.

Suppression of Schottky Gate-Leakage Current

AlGaN/GaN HEMTs always show much higher reverse gate leakage currents than the values theoretically predicted by the thermionic-emission (“TE”) model. The higher gate currents degrade the device's noise performance and raise the standby power consumption. In particular, forward gate currents limit the gate input voltage swing, hence the maximum drain-current. Other approaches have been attempted to suppress gate currents of AlGaN/GaN HEMTs. These efforts include using the gate metal with higher work function, using copper, modifying the HEMTs structure (such as adding a GaN cap), or diversion to metal-insulator-semiconductor heterostructure field-effect transistors (MISHFETs). In the CF₄ plasma-treated AlGaN/GaN HEMTs of the present innovations, suppressions of gate currents in both reverse and forward bias regions can be achieved. Gate-current suppressions show dependencies on CF₄ plasma-treatment conditions.

FIGS. 14A and 14B shows gate currents of AlGaN/GaN HEMTs with different CF₄ plasma treatments. FIG. 14B is the enlarged plot of the forward gate bias region. In reverse bias region, compared to the conventional HEMT without CF₄ plasma treatment, the gate-leakage currents of all the CF₄ plasma-treated AlGaN/GaN HEMTs decreased. At V_(g)=−20 V, the gate-leakage current drops by more than four orders of magnitude from 1.2×10⁻² A/mm for conventional HEMT to 7×10⁻⁷ A/mm for the AlGaN/GaN HEMT plasma treated at 200 W, 60 seconds. In the forward region, the gate currents of all the CF₄ plasma-treated AlGaN/GaN HEMTs also decrease. As a result, the turn-on voltages of the gate Schottky diode are extended, and the gate input voltages swings are increased. Using 1 mA/mm as the criterion, the turn-on voltage of the gate Schottky diode increases from 1 V for conventional HEMT to 1.75 V for the CF₄ plasma-treated AlGaN/GaN HEMT at 200 W for 60 seconds.

The suppression of the gate-leakage current in the CF₄ plasma-treated AlGaN/GaN HEMT can be explained as follows. During CF₄ plasma treatment, fluorine ions are incorporated into the AlGaN layer. These ions with a strong electronegativity act as immobile negative charges that cause the upward conduction-band bending in the AlGaN barrier layer due to the electrostatic induction effect. Thus, an additional barrier height φ_(F), as shown in FIG. 23 is formed, and the effective metal-semiconductor barrier height is increased from φ_(B) to φ_(B)+φ_(F). This enhanced barrier height can effectively suppress the gate Schottky diode current in both reverse and forward bias regions. With higher plasma power and longer treatment time, the fluorine ion concentration in the AlGaN layer increases, and the effective barrier height is raised further, leading to a more significant gate-current suppression. In FIG. 9 the effective barrier heights and ideality factors that were extracted from the forward region of the measured gate currents by using the TE model are detailed. The effective barrier height of conventional HEMT is 0.4 eV, while the effective barrier height increased to 0.9 eV for the CF₄ plasma-treated HEMT at 200 W for 60 seconds. The effective barrier heights of the CF₄ plasma-treated HEMT also show a trend of increase with the plasma power and treatment time, except for the HEMT treated at 150 W for 20 seconds, which has a relatively higher effective barrier height. This exception is thought to be due to the process variations. The fact that the extracted effective barrier height is much lower than the theoretically predicted values and very large ideality factors (>2.4) indicates that the gate currents of fabricated AlGaN/GaN HEMTs are not dominated by teh TE mechanism but other mechanisms, such as vertical tunneling, surface barrier thinning, and trap-assisted tunneling. Thus, the barrier heights and ideality factors, which are extracted by using the TE model, are not accurate. Nevertheless, they provide sufficient qualitative information for explaining the mechanism of the gate-current suppression in CF₄ plasma-treated AlGaN/GaN HEMTs.

Dynamic I-V characterizations were conducted by using an Accent DIVA D265 system to investigate the effects of CF₄ plasma treatment of drain-current dispersion. The pulse width is 0.2 μs and the pulse separation is 1 ms. The quiescent point is at VGS slightly (˜0.5 V) below the pinch-off and V_(DS)=15 V. Compared to static I-V characteristics, the maximum drain-current of conventional D-mode HEMT dropped by 63%, while that of E-mode HEMT with CF₄ plasma treatment at 150 W for 150 seconds dropped by 6%.

The alleviation of drain-current drops for E-mode HEMT is likely due to a raised gate bias of the quiescent point (V_(GS)=0 V for E-mode HEMT, V_(GS)=−4.5 V for D-mode HEMT).

RF Small-Signal Characteristics

On-wafer small-signal RF characterization of the fabricated AlGaN/GaN HEMTs were carried out at the frequency range of 0.1-39.1 GHz using Cascade microwave probes and an Agilent 8722ES network analyzer. Open-pad de-embeddings with the S-parameters of dummy pads were carried out to eliminate a parasitic capacitance of the probing pads. The current gain and maximum stable gain/maximum available gain (MSG/MAG) of all devices with 1-μm long gate were derived from the de-embedded S-parameters as a function of frequency. The current cutoff frequency (f_(t)) and maximum oscillation frequency (f_(max)) were extracted from current gains and MSG/MAGs at unit gain. It has been observed that the intrinsic f_(t) and f_(max) are generally 10-15% higher than the extrinsic ones without the de-embeddings process. The dependencies of f_(t) and f_(max) on the gate bias are shown in FIG. 15 for the E-mode HEMT. Both f_(t) and f_(max) are relatively constant at both low and high gate bias, indicating a good linearity. FIG. 16 lists f_(t) and f_(max) of all samples. For the conventional HEMT, f_(t) and f_(max) are 13.1 and 37.1 GHz, while for the CF₄ plasma-treated HEMTs, f_(t) and f_(max) are approximately 10 and 34 GHz, slightly lower than that of the conventional HEMT, except for the HEMT treated at 150 W for 60 seconds. This higher f_(t) and f_(max) in the 150 W/60 second device are consistent with the higher gm presented before, and are attributed to a material non-uniformity and process variation. The slightly lower f_(t) and f_(max) in the CF₄ plasma-treated HEMTs indicate that the post-gate RTA at 400° C. can effectively recover the 2DEG mobility degraded by the plasma treatment, but the recovery is less than 100%. It suggests that the optimization of the RTA temperature and time is needed to further improve the 2DEG mobility, while not degrading the gate Schottky contact.

MISHFETs

In another embodiment, E-mode Si₃N₄/AlGaN/GaN MISHFET were constructed with a two-step Si₃N₄ process which features a thin layer of Si₃N₄ (15 nm) under the gate and a thick layer of Si₃N₄ (about 125 nm) in the access region. Fluorine-based plasma treatment was used to convert the device from D-mode to E-mode. The E-mode MISHFETs with 1-μm long gate footprint exhibited a threshold voltage of 2 V, a forward turn-on gate bias of 6.8 V (compared to about a 3 V realized in E-mode AlGaN/GaN HMETs) and a maximum current density of 420 mA/mm.

The AlGaN/GaN HFET structure used in this letter was grown on (0001) sapphire substrates in an Aixtron AIX 2000 HT MOCVD system. The HFET structure consists of a 50-nm thick low temperature GaN nucleation layer, a 2.5-μm thick not-intentionally doped GaN buffer layer, and an AlGaN barrier layer with nominal 30% Al composition. The barrier layer is composed of a 3-nm undoped spacer, a 16-nm carrier supplier layer doped at 2×10¹⁸ cm⁻³, and a 2-nm undoped cap layer. The capacitance-voltage (“C-V”) measurement by mercury probe yields an initial threshold voltage of −4 V for this sample. The process flow is illustrated in FIGS. 17A through 17F. The device mesa is formed using Cl₂/He plasma dry etching in an STS ICP-RIE system followed by the source/drain ohmic contact formation with Ti/Al/Ni/A (20 nm/150 nm/50 nm/80 nm) annealed at 850° C. for 30 seconds, as shown in FIG. 17A. Then, the first Si₃N₄ layer (about 125 nm) is deposited on the sample by plasma enhanced chemical vapor deposition (PECVD) as in FIG. 17B. After gate windows with 1-μm length are opened by photolithography, the sample was put in an RIE system under CF₄ plasma treatment, which removed the Si₃N₄ and incorporated fluorine ions in the AlGaN. The RF power of the plasma was 150 W, as shown in FIG. 17C. The gas flow was controlled to be 150 sccm, and the total etching and treatment time is 190 seconds. After removing the photoresist, the second Si₃N₄ film (about 15 nm) was deposited by PECVD to form the insulating layer between gate metal and AlGaN as in FIG. 17D. Subsequently, the Si₃N₄ layer was patterned and etched to open windows in the source and drain ohmic contact regions, as shown in FIG. 17E. Next, the 2-μm long gate electrodes were defined by photolithography followed by e-beam evaporation of Ni/Au (˜50 nm/300 nm) and liftoff as in FIG. 17F. To ensure that the gate electrode covers the entire plasma-treated region, the metal gate length (2 μm) was chosen to be larger than the treated gate area (1 μm), leading to T-gate configuration. The gate overhang in the source/drain access regions is insulated from the AlGaN layer by thick Si₃N₄ layer, keeping the gate capacitances at low level. Finally, the whole sample was annealed at 400° C. for 10 minutes to repair the plasma-induced damage in the AlGaN barrier and channel. Measured from the foot gate, the gate-source and gate-drain spacings are both 1.5 μm. The E-mode MISHFETs are designed with gate width of 10 μm for dc testing and 100 μm for RF characterizations.

The constructed device was then characterized. The DC output characteristics of the E-mode MISHFETs are plotted in FIG. 18. The devices exhibit a peak current density of about 420 mA/mm, an ON-resistance of about 5.67 Ω·mm and a knee voltage of about 3.3 V at V_(gs)=7 V. FIG. 19A shows the transfer characteristics of the same device with 1×10-μm gate dimension. It can be seen that the V_(th) is about 2 V, indicating a 6-V shift of V_(th) (compared to a conventional D-mode HFET) achieved by the insertion of the Si₃N₄ insulator and plasma treatment. The peak transconductance gm is about 125 mS/mm. FIG. 19B shows the gate leakage current at both the negative bias and forward bias. The forward bias turn-on voltage for the gate is about 6.8 V, providing a much larger gate bias swing compared to the E-mode HFETs. Pulse measurements were taken on the E-mode MISHFETs with 1×100-μm gate dimensions with a pulse length of 0.2 μs and a pulse separation of 1 ms. The quiescent bias point is chosen at V_(GS)=0 V (below V_(th)) and V_(DS)=20 V. FIG. 20 shows that the pulsed peak current is higher than the static one, indicating no current collapse in the device. The static maximum current density of the large device with a 100-μm gate width is about 330 mA/mm, smaller than the device with 10-μm gate width (about 420 mA/mm). The lower peak current density in the larger device is due to the self-heating effect that lowers the current density. Since little self-heating occurs during pulse measurements, the maximum current for the 100-μm wide device can reach the same level as the 10-μm wide device. On wafer small-signal RF characteristics were performed from 0.1 to 39.1 GHz on the 100-μm wide E-mode MISHFETs at V_(DS)=10 V. As shown in FIG. 21, the maximum current gain cutoff frequency (f_(T)) and power gain cutoff frequency (f_(max)) are 13.3 and 23.3 GHz, respectively. When the gate bias is 7 V, the small-signal RF performance does not significantly degrade, with an f_(T) of 13.1 GHz and an f_(max) of 20.7 GHz, indicating that the Si₃N₄ insulator offers an excellent insulation between gate metal and semiconductor.

Models

A theoretical characterization model was developed for some of the present innovations. For a conventional AlGaN/GaN HEMT with silicon modulation doped layer, as shown in FIG. 7, the polarization charges need to be taken into account in the calculation of HEMTs threshold voltage. Modified from a generally used formed by taking into account the effects of charge polarization, surface and buffer traps, the threshold voltage of the AlGaN/GaN HEMT can be expressed as:

$\begin{matrix} {V_{th} = {{\phi_{B}/e} - {d\;{\sigma/ɛ}} - {\Delta\;{E_{C}/e}} + {E_{f\; 0}/e} - {\frac{e}{ɛ}{\int_{0}^{d}\ {{\mathbb{d}x}{\int_{0}^{x}{{N_{si}(x)}\ {\mathbb{d}x}}}}}} - {e{{\mathbb{d}N_{st}}/ɛ}} - {{eN}_{b}/{C_{b}.}}}} & (1) \end{matrix}$ Where the parameters are defined as follows:

-   -   Φ_(B) is the metal-semiconductor Schottky barrier height.     -   σ is the overall net (both spontaneous and piezoelectric)         polarization charge at the barrier-AlGaN/GaN interface.     -   d is the AlGaN barrier/layer thickness.     -   N_(si)(x) is the silicon-doping concentration.     -   ΔE_(c) is the conduction-band offset at the AlGaN/GaN         heterostructure.     -   E_(ƒ0) is the difference between the intrinsic Fermi level and         the conduction band edge of the GaN channel.     -   ε is the dielectric constant of AlGaN.     -   N_(st) is the net-charged surface traps per unit area.     -   N_(b) is the effective net-charged buffer traps per unit area.     -   C_(b) is the effective buffer-channel capacitance per unit area.         The last two terms in equation (1) describe the effects of the         surface traps and buffer traps, respectively. The AlGaN surface         is at x=0, and the direction pointing to the channel is the         positive direction for the integration. To represent the devices         described above, immobile negative charges are introduced into         the AlGaN barrier layer under the gate. Because of electrostatic         induction, these immobile negative charges can deplete 2DEG in         the channel, raise the energy band, and hence modulate V_(th).         Including the effect of the negative charges confined in the         AlGaN barrier, the modified threshold voltage from equation (1)         is given by:

$\begin{matrix} {V_{th} = {{\phi_{B}/e} - {d\;{\sigma/ɛ}} - {\Delta\;{E_{C}/e}} + {E_{f\; 0}/e} - {\frac{e}{ɛ}{\int_{0}^{d}\ {{\mathbb{d}x}{\int_{0}^{x}{\left( {{N_{si}(x)} - {N_{F}(x)}} \right)\ {\mathbb{d}x}}}}}} - {e{\mathbb{d}N_{st}^{\prime}}\text{/}ɛ} - {{eN}_{b}/{C_{b}.}}}} & (2) \end{matrix}$ The positive-charge distribution profile N_(si)(x) is replaced by the net charge distribution N_(si)(x)−N_(F)(x), where N_(F)(x) is the concentration of the negatively charged fluorine ion. The surface-trap density (N_(si)) could be modified by the plasma treatment.

By applying Poisson's equation and Fermi-Dirac statistics, a simulation was made of the conduction-band profiles and the electron distributions of AlGaN/GaN HEMT structures with and without fluorine ions incorporated in AlGaN layer. Both structures have the same epitaxial structure, shown in FIG. 7. For the fluorine ions incorporated HEMT structure, the negatively charged fluorine ions' profile was extracted for SIMS measurement results of the fluorine atoms' distribution of an AlGaN/GaN HEMT structure that was treated by CF₄ plasma at 150 W for 150 s and converted to an E-mode HEMT. The stimulated conduction band diagrams at zero gate bias were plotted in FIGS. 22 and 23 For the simulated conduction band E-mode HEMT, as shown in FIG. 22 the fluorine concentration is approximated by using a linear distribution that the peak fluorine concentration is 3×10¹⁹ cm⁻³ at the AlGaN surface, and the fluorine concentration is assumed to be negligible at the AlGaN/GaN interface. A total fluorine ion sheet concentration of about 3×10¹³ cm⁻² is sufficient to not only compensate for the doping (about 3.7×10¹⁸ cm²) in the AlGaN barrier but also to compensate for the piezoelectric and spontaneous polarization-induced charges (about 1×10¹³ cm⁻²). Two significant features can be observed. First, compared to the untreated AlGaN/GaN HEMT structure, the plasma-treated structure has its 2DEG channel's conduction-band minimum above Fermi level, indicating a completely depleted channel and E-mode HEMT. As shown in the electron profiles in FIG. 24, there are no electrons in the channel under the zero gate bias in the plasma-treated structure, indicating an E-mode HEMT operation. Second, the immobile negatively charged fluorine ions cause an upward bending of the conduction band, especially in AlGaN barrier, yielding an additional barrier height φF, as shown in FIG. 23 Such an enhanced barrier can significantly suppress the gate Schottky diode current of AlGaN/GaN HEMT in both the reverse and forward bias regions.

According to a disclosed class of innovative embodiments, there is provided: a semiconductor active device, comprising: first and second conductive source/drain regions, separated by a channel consisting essentially of a Group III nitride compound; a wider-bandgap semiconductor layer overlying said channel, which also consists essentially of a Group III nitride compound, and which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap layer, and is capacitively coupled to said channel to control conduction therein; wherein said wider-bandgap layer comprises fluorine ions which shift the threshold voltage of said channel, as seen by said gate, sufficiently that said channel operates in enhancement mode.

Also provided is a device as above, wherein said wider-bandgap layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume.

Also provided is a device as above, wherein said wider-bandgap layer has inhomogeneous doping.

Also provided is a device as above, further comprising a gate insulator layer below said gate electrode.

Also provided is a device as above, wherein said channel layer is GaN, and said wider-bandgap layer is AlGaN.

Also provided is a device as above, wherein said wider-bandgap layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume.

Also provided is a device as above, wherein said gate electrode overlies a planar portion of said wider-bandgap semiconductor, without any recess etch.

Also provided is a device as above, wherein said wider-bandgap semiconductor includes more than 10¹⁸ cm⁻³ of fluorine atoms.

According to a disclosed class of innovative embodiments, there is provided: a semiconductor active device, comprising: first and second condutive source/drain regions, separated by a channel consisting essentially of a Group III nitride compound; a wider-bandgap semiconductor layer overlying said channel, which also consists essentially of a Group III nitride compound, and which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap layer, and is capacitively coupled to said channel to control conduction therein; wherein said wider-bandgap layer comprises fluorine ions in a dosage of more than 10¹³ cm⁻².

Also provided is a device as above, wherein said wider-bandgap layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume as said wider-bandgap layer.

Also provided is a device as above, further comprising a gate insulator layer below said gate electrode.

Also provided is a device as above, wherein said channel layer is GaN, and said wider-bandgap layer AlGaN.

Also provided is a device as above, wherein said gate electrode overlies a planar portion of said wider-bandgap semiconductor, without any recess etch.

According to a disclosed class of innovative embodiments, there is provided: a semiconductor active device, comprising: first and second conductive souce/drain regions, connected by a channel, all consisting essentially of a Group III nitride semiconductor compound; a wider-bandgap semiconductor layer, overlying and lattice matched to said channel, which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap layer, and is capacitively coupled to said channel to control conduction therein; wherein said wider-bandgap layer comprises fluorine ions in a concentration which shifts the threshold voltage of said channel, as seen by said gate, by at least 100 millivolts.

Also provided is a device as above, further comprising a gate insulator layer below said gate electrode.

Also provided is a device as above, wherein said channel layer is GaN, and said wider-bandgap layer is AlGaN.

Also provided is a device as above, wherein said gate electrode overlies a planar portion of said wider-bandgap semiconductor, without any recess etch.

According to a disclosed class of innovative embodiments, there is provided: a semiconductor active device, comprising: first and second conductive source/drain regions, separated by a semiconductor channel consisting primarily of GaN; a wider-bandgap semiconductor layer overlying said channel, and consisting primarily of AlGaN semiconductor, and having a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap layer, and is capacitively coupled to said channel to control conduction therein; wherein said wider-bandgap layer comprises fluorine ions in a dosage of more than 10¹³ cm⁻².

Also provided is a device as above, further comprising a gate insulator layer below said gate electrode.

Also provided is a device as above, wherein said gate electrode overlies a planar portion of said wider-bandgap semiconductor, without any recess etch.

Also provided is a device as above, wherein said wider-bandgap layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume.

Also provided is a device as above, wherein said wider-bandgap layer has inhomogeneous doping.

According to a disclosed class of innovative embodiments, there is provided: a method of operating a III-N semiconductor active device, comprising the actions of: controlling accumulation/depletion of majority carriers in a III-N semiconducting channel, using capacitance coupling through a wider-bandgap III-N semiconductor layer which overlies said channel layer, and which has a higher fraction of aluminum than does said channel layer; while applying a constant bias to said accumulation/depletion, by a fixed charge component provided by substitutional impurities in said wider-bandgap semiconductor layer, whereby said channel layer can operate in enhancement mode.

Also provided is a method as above, wherein said wider-bandgap layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume.

Also provided is a method as above, wherein said gate electrode is separated from said wider-bandgap layer by a gate insulator layer.

Also provided is a method as above, wherein said channel layer is GaN, and said wider-bandgap layer AlGaN.

According to a disclosed class of innovative embodiments, there is provided: a process for fabricating a semicondutor active device, comprising the actions of: a) introducing fluorine into a vertically inhomogeneous semicondutor layer having the general composition of Al_(x)M_(1-x)Y, where M is predominantly Ga and Y is pridominantly N, and the Al fraction is higher near a surface of said layer; and b) positioning a gate electrode, in proximity to said surface, over a channel area of said semiconductor layer, to control conduction therethrough; wherein said action a) shifts the threshold voltage of said channel as seen by said gate electrode.

Also provided is a process as above, wherein said semiconductor layer is an AlGaN/GaN layered structure.

Also provided is a process as above, wherein said action (a) also introduces fluorine into device isolation zones.

Also provided is a process as above, wherein said action (b) is self-aligned to at least some locations where fluorine was introduced in said action (a).

Also provided is a process as above, wherein said semiconductor layer is an epitaxial structure comprising a nucleation layer of GaN or AIN, a buffer layer of GaN of AlGaN, a GaN channel, and an AlGaN barrier.

Also provided is a process as above, further comprising the additional action of forming sources and drains which can provide conduction through said channel, by depositing multiple metal layers and rapid thermal annealing; wherein said metals are selected from the group consisting of Ti, Al, Ni, and Au.

Also provided is a process as above, wherein said introducing action (a) uses a feed gas selected from the group consisting of CF₄, SF₆, BF₃, and mixtures thereof.

Also provided is a process as above, wherein said action (b) deposits at least one metal selected from the group consisting of Ti, Al, Ni, and Au, followed by lift-off.

Also provided is a process as above, further comprising the subsequent action of depositing a passivation material selected from the group consisting of silicon nitride, silicon oxide, polymide, and benzocyclobutene.

Also provided is a process as above, further comprising the subsequent action of a final thermal annealing at approximately the hightest temperature which will not change the Schottky barrier below the gate. According to a disclosed class of innovative embodiments, there is provided: a process for fabricating a semicondutor active device, comprising the actions of: under vacuum conditions, fluoro-etching a dielectric layer over at least some desired channel locations in a vertically inhomogeneous semiconductor layer having the general composition of Al_(x)M_(1-x)Y, where M is predominantly Ga and Y is predominantly N, and the Al fraction is higher near a surface of said layer; and after said fluoro-etch reaches and stops on said semiconductor layer, continuing fluoro-etch conditions thereafter, to introduce more than 10¹² fluorine atoms per square centimeter into said semiconductor layer under plasma bombardment conditions; and positioning a gate electrode, in proximity to said surface, over a channel area of said semiconductor layer, to control conduction therethrough; wherein said fluorine atoms shift the threshold voltage of said channel as seen by said electrode.

Also provided is a process as above, wherein said semiconductor layer is an AlGaN/GaN layered structure.

Also provided is a process as above, wherein said semiconductor layer is an epitaxial structure comprising a nucleation layer of GaN or AlN, a buffer layer of GaN or AlGaN, a GaN channel, and an AlGaN barrier.

Also provided is a process as above, further comprising the additional action of forming sources and drains which can provide conduction through said channel, by depositing multiple metal layers and rapid thermal annealing; wherein said metals are selected from the group consisting of Ti, Al, Ni, and Au.

Also provided is a process as above, wherein said gate electrode is formed by depositing at least one metal selected from the group consisting of Ti, Al, Ni, and Au, followed by lift-off.

Also provided is a process as above, further comprising the subsequent action of depositing a passivation material selected from the group consisting of silicon nitride, silicon oxide, polyimide, and benzocyclobutene.

Also provided is a process as above, further comprising the subsequent action of a final thermal annealing at approximately the highest temperature which will not change the Schottky barrier below the gate.

Modifications and Variations

As will be recognized by those skilled in the art, the innovative concepts described in the present application can be modified and varied over a tremendous range of applications, and accordingly the scope of patented subject matter is not limited by any of the specific exemplary teachings given.

While the above example describes a leteral device, it is also contemplated that the various disclosed inventions can be used in merged devices including a lateral transistor element.

It is also contemplated that the disclosed inventions can be applied to some classes of vertical devices with appropriate changes.

For example, minor variations in the semiconductor composition, e.g. use of a phosphonitride instead of a pure nitride, or use of an Al_(x)Ga_((1−x))N over Al_(y)Ga(1−y)N heterostructure for basic HEMT structure, are contemplated as alternatives.

The present innovations provide users with the capability of making single voltage supply RFIC and MMIC. It also provides users a monolithic integration technology for implementing GaN-based digital integrated circuits that are needed for high temperature electronics.

For example, on the various device structures shown, a variety of materials can optionally be used for gate electrodes (taking into account any resulting differences in work function). In one contemplated class of embodiments, gate materials with different work functions can be used in combination with the trapped sheet charge layer provided by various embodiments described above. Similarily, various changes or substitutions can be made in the epitaxial layer doping.

Similarily, as noted above, various materials can optionally be used for the substrate.

Additional general background, which helps to show variations and implementations, may be found in the following publications, each and every one of which is hereby incorporated by reference:

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None of the description in the present application should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope: THE SCOPE OF PATENTED SUBJECT MATTER IS DEFINED ONLY BY THE ALLOWED CLAIMS. Moreover, none of these claims are intended to invoke paragraph six of 35 USC section 112 unless the exact words “mean for” are followed by a participle.

The claims as filed are intended to be as comprehensive as possible, and NO subject matter is intentionally relinquished, dedicated, or abandoned. 

1. A Group III nitride semiconductor active device, comprising: first and second conductive source/drain regions, separated by a channel consisting essentially of a Group III nitride compound; a wider-bandgap semiconductor layer, which is overlying said channel, which wider-bandgap semiconductor layer also consists essentially of a Group III nitride compound, and which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap semiconductor layer, and which conductive gate electrode is capacitively coupled to said channel to control conduction therein; and wherein said wider-bandgap semiconductor layer comprises negatively charged fluorine ions which sufficiently shift the threshold voltage of said channel, as seen by said gate, that said channel has a positive threshold voltage at zero supplied gate voltage.
 2. The device of claim 1, wherein said wider-bandgap semiconductor layer comprises dopant atoms, said channel has fewer than one-tenth as many dopant atoms per unit volume as that of said wider-bandgap semiconductor layer.
 3. The device of claim 1, wherein said wider-bandgap semiconductor layer has inhomogeneous doping.
 4. The device of claim 1, further comprising a gate insulator layer below said conductive gate electrode.
 5. The device of claim 1, wherein said channel layer is Gallium-Nitride (GaN), and said wider-bandgap semiconductor layer is Aluminum-Gallium-Nitride (AlGaN).
 6. The device of claim 5, wherein said wider-bandgap semiconductor layer comprises dopant atoms, said channel has fewer than one-tenth as many dopant atoms per unit volume as that of said wider-bandgap semiconductor layer.
 7. The device of claim 1, wherein said conductive gate electrode overlies a planar portion of said wider-bandgap semiconductor layer, without any recess etch.
 8. The device of claim 1, wherein said negatively charged fluorine ions are more than 10¹⁸ ions per cubic centimeter (cm⁻³) in concentration.
 9. A Group III nitride semiconductor active device, comprising: first and second conductive source/drain regions, separated by a channel consisting essentially of a Group III nitride compound; a wider-bandgap semiconductor layer, which is overlying said channel, which wider-bandgap semiconductor layer also consists essentially of a Group III nitride compound, and which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap semiconductor layer, and which conductive gate electrode is capacitively coupled to said channel to control conduction therein; and wherein said wider-bandgap semiconductor layer comprises more than 10¹⁸ negatively charged fluorine ions per cubic centimeter (cm⁻³).
 10. The device of claim 9, wherein said wider-bandgap semiconductor layer comprises dopant atoms, and said channel has fewer than one-tenth as many dopant atoms per unit volume as said wider-bandgap semiconductor layer.
 11. The device of claim 9, further comprising a gate insulator layer below said conductive gate electrode.
 12. The device of claim 9, wherein said channel layer is Gallium-Nitride (GaN), and said wider-bandgap semiconductor layer is Aluminum-Gallium-Nitride (AlGaN).
 13. The device of claim 9, wherein said conductive gate electrode overlies a planar portion of said wider-bandgap semiconductor layer, without any recess etch, and said fluorine ion profile and said channel structure is adjusted by a post-gate thermal annealing.
 14. A Group III nitride semiconductor active device, comprising: first and second conductive source/drain regions, connected by a channel, all of the first and second conductive source/drain regions and the channel comprising essentially a Group III nitride semiconductor compound; a wider-bandgap semiconductor layer, overlying and lattice matched to said channel, which has a higher fraction of aluminum than does said channel; a conductive gate electrode which lies above said wider-bandgap semiconductor layer, and is capacitively coupled to said channel to control conduction therein; and wherein said wider-bandgap semiconductor layer comprises negatively charged fluorine ions in a concentration which shifts the threshold voltage of said channel, as seen by said gate, by at least 100 millivolts.
 15. The device of claim 14, further comprising a gate insulator layer below said conductive gate electrode.
 16. The device of claim 14, wherein said channel layer is Gallium-Nitride (GaN), and said wider-bandgap semiconductor layer is Aluminum-Gallium-Nitride (AlGaN).
 17. The device of claim 14, wherein said conductive gate electrode overlies a planar portion of said wider-bandgap semiconductor layer, without any recess etch, and said Group III nitride semiconductor active device having reduced plasma-induced damage based in part on a post-gate thermal annealing treatment at 400-800 degrees Celsius (° C.).
 18. The device of claim 1, wherein said Group III nitride semiconductor active device having reduced plasma-induced damage based in part on a post-gate thermal annealing. 